In almost all digital data transmission systems, the receiver is required to sample the received waveform once per symbol in a relatively small interval in order to minimize the bit-error-rate (BER). If the transmission technique is optimized for bandwidth and power efficiency, a sampling instance corresponding to-the maximum of the "eye-opening" (a transition from a 0 to a 1 looks like an eye) usually provides the best performance.
For continuous transmission systems, the sampling clock is typically obtained from a clock recovery loop which derives the timing from zero crossings occurring during data transitions. The clock recovery loop is typically a phase-locked-loop (PLL). The loop bandwidth B of the PLL is chosen to maintain the steady-state jitter and initial acquisition time within a reasonable range.
For burst mode transmission, it is 104 is necessary to transmit a preamble which contains a sufficient number of data transitions for the clock recovery loop to detect before receiving valid data. Typically, the Preamble contains a sequence of alternating zeroes and ones (01010101 . . . ). The length of this sequence is typically three times the loop time constant, 1/B, because a typical PLL takes this duration to settle.
A conventional burst mode sampling timing acquisition circuit is shown in FIG. 1. A received digital signal burst is input to the circuit at input terminal 106. The burst has been transmitted from a transmitter over an analog transmission channel thus rendering the originally digital burst into an analog form. The analog-to-digital (A/D) converter 100 performs the operation of reconverting the transmitted signal burst back into the digital format.
The frequency of the sampling clock which drives the A/D 100 (i.e., the sampling rate) is known at the receiver, since a standard rate is used. However, the phase of the clock is unknown at the receiver and the purpose of the circuit of FIG. 1 is to acquire the correct sampling phase, hereinafter referred to as the correct sampling timing phase.
As discussed above, in conventional systems a preamble composed of an alternating sequence of zeroes and ones is attached to the front end of a digital signal burst in order to provide a known signal burst portion for use in sampling timing (sampling phase) acquisition. This preamble must have a length, in conventional systems, of at least 3/B (where B is the bandwidth of the PLL), since the PLL requires that much time to settle.
After channel filtering is carried out by well-known techniques in order to remove other signals and out-of-band noise from the received signal burst, the burst is input to the circuit of FIG. 1 at terminal 106. The burst is then sampled by the A/D converter 100 which operates at an expected sampling rate. The A/D converter 100 samples the received signal twice per symbol. The demultiplexer 101 separates the samples and sends the odd samples, for example, onto demultiplexer output line 109, and the even samples, for example, onto demultiplexer output line 110.
The 10101010 . . . sequence of the preamble, if repeated for a sufficiently long duration, produces a sinusoidal waveform after channel filtering. This is because the channel filters are usually designed to be very tight in order to minimize the noise, and all higher order (third, fifth, etc.) harmonics are removed by the channel. This sinusoidal waveform has a frequency equal to half of the symbol rate. If the symbol timing is correct, four samples per cycle are obtained, two at zero-crossings, and two at the peaks.
The samples output onto the demultiplexer output line 110 represent samples which, at the correct sampling timing phase, would represent the peaks (both positive and negative in amplitude) of the sinusoidal wave mentioned above. These samples are sent to a transition detector 102 which outputs one of three values 1, 0, or +1 depending on whether the sample input to the transition detector 102 is closer to the maximum negative peak, the zero level or the maximum positive peak, respectively. The samples output from the demultiplexer on demultiplexer output line 109 correspond, at the correct sampling timing phase, to the zero crossing points of the above-mentioned sinusoidal wave.
A multiplier 103 receives as inputs the samples output from the demultiplexer on demultiplexer output line 109 and the output 111 of the transition detector 102. The output 112 of the multiplier 103 represents the amount of deviation from the correct sampling timing phase for the presently used sampling clock. The above-mentioned circuitry tests the samples exactly one symbol time apart for data transitions. If a transition occurs, an error voltage proportional to the sample near the transition (the sample output from the demultiplexer 101 onto demultiplexer output line 109) is fed through a low pass filter (LPF) 104 to a voltage-controlled-oscillator (VCO) 105.
The output of the VCO 105 is fed back to be used by the A/D converter 100 as a sampling clock signal. Thus, when the error voltages output from the multiplier 103 are sent to the VCO 105 through the LPF 104, these error voltages modify the phase of the sampling clock of the A/D converter so as to place the phase of the sampling clock closer to the correct sampling timing phase.
As mentioned above, in order to acquire the correct sampling timing phase by the above conventional system, a preamble of length 3/B is required. For certain burst messages, such as those generated by interactive computer-to-computer communications, network control, signaling, and acknowledgements, bursts lengths are inherently short. A long preamble adversely reduces the throughput of the system. This preamble length is the main disadvantage of the PLL method (FIG. 1) of obtaining the correct sampling timing phase.
An alternative approach uses a tuned filter. The received signal is first squared to remove modulation. During data transitions, the squared waveform has envelope fluctuation. A harmonic of the envelope fluctuation at the symbol rate, R.sub.s is obtained by passing this signal through a filter with noise bandwidth B and center frequency are equal to the symbol rate. The squaring operation, however, causes a loss of 6 dB in terms of signal-to-noise ratio. The standard deviation of the clock jitter in steady-state equals 1/.sqroot.E.sub.s R.sub.s /2N.sub.o E in radians. Typically, the tuned filter needs a preamble of length 1.25/B which is only 40 percent of that required by the PLL approach described above with respect to FIG. 1.
The tuned filter approach suffers from other drawbacks. Namely, narrow bandpass filters, needed for use in the tuned filter approach, usually require expensive stable precision components such as high-Q inductors.